Novel strained superjunction VDMOS

Abstract

In this paper, we have proposed novel strained superjunction (s-SJ) vertical double diffused MOS (VDMOS). Through channel engineering, we have introduced strain effects in s-SJ device using thin separate p-type silicon–germanium (p-SiGe) layer over silicon p-pillar. Further, we have designed process flow for the possible fabrication of s-SJ VDMOS. The proposed s-SJ devices fitted with less input capacitance (Cin) and 1.2∼3 times higher output current density than conventional SJ VDMOS. Therefore, 40% less gate charge (Qg) is required to turn-on the s-SJ VDMOS and RonA is optimized in between 12% and 46%.