Novel Strained CMOS Devices with STI Stress Buffer Layers

Abstract

STI stress buffer techniques including sidewall stress buffer and channel surface buffer layers are developed to reduce the impact of compressive STI stress on the mobility of advanced N-MOS devices. For L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> down to 35 nm, 7% improvement of drive current at N-MOS has been achieved, while no degradation at P-MOS drive current and maintaining the same junction leakage at both N-MOS and P-MOS. A stress relaxation model with simulation is proposed to account for the enhanced transportation characteristics.