Abstract

A novel snapback-free silicon-controlled rectifier (SFSCR) with P-type Zener implantation (ZP) is developed in a 0.5- $\mu \text{m}$ bipolar CMOS DMOS technology for latch-up immune high-voltage (HV) electrostatic discharge (ESD) protection. The inherent snapback of SCR is successfully suppressed by the novel ZP technique. But, it also brings about a serious degradation in failure current ( ${I}_{\textsf {t2}}$ ) when compared with the regular low holding voltage ( ${V}_{h}$ ) device. In order to mitigate such degradation, a novel layout terminal is proposed. According to the transmission-line pulse test results, ${I}_{\textsf {t2}}$ of the SFSCR with new layout is increased by 58.5%, while the ON-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) is reduced by 48.7% under the same layout area. By comprehensive comparison, the SFSCR is proved to be a potential HV ESD solution.

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