Novel Si ion implantation technique for improving the radiation hardness of SOI pseudo-MOS transistor

Abstract

The pseudo-MOS transistor is a quick and effective technique for characterizing the electrical properties of silicon-on-insulator (SOI) wafer. We investigated the total ionizing dose (TID) response of pseudo-MOS transistors fabricated on SOI wafers hardened by single or multiple step Si ion implantation. It is demonstrated that the two Si ion implantation methods can both improve the radiation hardness of SOI wafers owing to the generation of deep electron traps in the buried oxide (BOX). However, the lattice damage of top silicon film caused by the single step implantation compared with the multiple degenerates the electrical properties of transistors, especially for the sub-threshold swing. The high resolution transmission electron microscopy (HRTEM) was used to observe the lattice quality.