Novel robust optimization method of lithographic conditions for correlative multilayers beyond 65 nm node

Abstract

Parameter optimization is a key issue to develop low-k1 lithography processes, in which the number of error factors and that of critical patterns have been increasing. In order to attain a target performance of integrated circuits under numerous error factors (or noise factors), this paper describes a novel method to optimize various parameters simultaneously. The parameters include not only those related to exposure conditions such as NA, sigma and etc, but also include those related to layout restrictions for various patterns. The optimization method we applied is based on the Taguchi method for robust design experiments, which uses orthogonal arrays with a single criterion, which is called “signal-to-noise (SN) ratio”, for optimization. The optimization is performed so as to maximize the SN ratio for a pattern critical-dimension (CD) or the SN ratio for an operating window such as the open-to-short operating window of electric connections. Two cases of optimization are reported in this article, one for an intermediate metal layer in a 45 nm-node device, and the other for a via-hole layer connected to the metal layer. Any type of noise factors and critical patterns could be taken into account and an optimum set of parameters could be determined quickly and simultaneously by applying the method. The results demonstrate that this global optimization method is a very powerful tool to optimize multiple parameters in low-k1 lithography processes.