Novel Push-Push Frequency Doubler Concept

Abstract

This paper presents a novel push-push frequency doubler concept which can deliver high balanced output power. Two lumped couplers provide balanced quadrature input signaling for two doubler cells. As a result, the output signals of the two doubler cells form an inherently balanced output and a lossy output transformer can be avoided. Hence, higher output power and efficiency can be achieved. Moreover, high fundamental rejection and supply suppression with low LO leakage into other circuit blocks are further advantages. As a proof of concept, a K-band doubler is implemented in a 65 nm CMOS technology. At 0 dBm input power, the circuit delivers 4.3 dBm output power with more than 6 % PAE. The chip draws 24 mA from a 1.2 V supply and the total chip area is 0.85 × 0.55 mm2, The fundamental suppression is around 44 dBc. The concept is applicable to other technologies and frequencies as well.