Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference.

Jungsik Kim,Su-In Yi

doi:10.3390/mi12050584

Abstract

Minimizing the variation in threshold voltage (Vt) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize Vt variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., Lg: 31→24 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density.

Highlights

Due to the nature of NAND flash memory, which lacks the capability of random access [1] of NOR flash memory [2,3] or other memories such as DRAM (Dynamic RandomAccess Memory) and PCM (Phase Change Memory), reading and writing operations of one cell inevitably accompanies operations on the other cells simultaneously in a target NAND string [4,5]
Varying bias conditions depending on the word line (WL) number, due to the nature of high aspect ratio contact etching [11,12,13], need to be investigated by trial and error to meet the criteria of Vt variation in a tight schedule
In order to accumulate the prior experience on the operation scheme optimization toward the sustainable technique for future products, it is critically important to understand the correlation between the input and the output (Vt variation)

Summary

Introduction

Due to the nature of NAND flash memory, which lacks the capability of random access [1] of NOR flash memory [2,3] or other memories such as DRAM (Dynamic RandomAccess Memory) and PCM (Phase Change Memory), reading and writing operations of one cell inevitably accompanies operations on the other cells simultaneously in a target NAND string [4,5]. Varying bias conditions depending on the word line (WL) number, due to the nature of high aspect ratio contact etching [11,12,13], need to be investigated by trial and error to meet the criteria of Vt variation in a tight schedule. For this reason, the operation scheme optimization process heavily relies on the product engineers’ intuition or, recently, statistical approaches such as machine learning technology which can often neglect to understand the underlying charge transport physics [14,15]. In order to accumulate the prior experience on the operation scheme optimization toward the sustainable technique for future products, it is critically important to understand the correlation between the input (operation scheme) and the output (Vt variation)

Methods

Discussion

Conclusion