Abstract
A novel process to fabricate a vertical double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET) has been proposed. The etch rate of ion-beam exposed Si in a tetramethylammonium hydroxide (TMAH) solution was found to be significantly retarded. By utilizing this phenomenon and the orientation-dependent etching of the Si with a TMAH solution, a 16-nm-thick Si wall for a vertical channel of the DG MOSFET was successfully fabricated on the bulk Si substrate. By applying the etchback process, symmetrical poly-Si DG was formed on each side of the Si wall. A drain contact hole was opened self-aligned to the Si wall by combining a planarization and an etchback process with an electron-beam resist.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
