Novel Parity-Preserving Designs of Reversible 4-Bit Comparator

Abstract

Reversible logic has attracted much attention in recent years especially when the calculation with minimum energy consumption is considered. This paper presents two novel approaches for designing reversible 4-bit comparator based on parity-preserving gates, which can detect any fault that affects no more than a single logic signal. In order to construct the comparator, three variable EX-OR gate (TVG), comparator gate (CPG), four variable EX-OR gate block (FVGB) and comparator gate block (CPGB) are designed, and they are parity-preserving and reversible. Their quantum equivalent implementations are also proposed. The design of two comparator circuits is completed by using existing reversible gates and the above new reversible circuits. All these comparators have been modeled and verified in Verilog hardware description language (Verilog HDL). The Quartus II simulation results indicate that their circuits’ logic structures are correct. The comparative results are presented in terms of quantum cost, delay and garbage outputs.