Novel packaging and high-current pulse-switching of 1.0 cm<sup>2</sup> SiC SGTOs

Abstract

The U.S. Army Research Laboratory has been driving the advancement of high-voltage, high-current silicon carbide devices and packaging through collaborations with Cree, Inc. and Silicon Power Corp. This paper reports on 1.0 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Super-GTOs fabricated by Cree, packaged by Silicon Power, and evaluated under pulse conditions at the Army Research Laboratory. These semiconductor switches were utilized to rapidly discharge capacitive energy into a resistive load. The Super-GTOs were packaged in parallel pairs using low-inductance thinPak lids for 2.0 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> total silicon carbide area with high-voltage blocking capability up to 9.0 kV. The two-chip arrays were switched at three different pulse widths, ranging from 45μs to 75μs (full-width at half-maximum), up to peak current capability. The maximum current switched was 11.7 kA, corresponding to 8.0 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> over the mesa, with a 10-90% dI/dt of 1.5 kA/μs. Two arrays were also paralleled and switched to 18 kA with current sharing within 1%. Individually the arrays were also reliably switched up to 100 pulses. The results are encouraging for the device design and packaging techniques, and for the capability of paralleling many devices to reach higher pulse currents.