Abstract

Novel Optical Proximity Correction (OPC) flow using the new compact lithography model which predicts wafer patterns formed by the trim-mask lithography has been developed. The trim-mask lithography has been indispensable to manufacture the random-logic devices using the leading-edge processes which require double patterning technology (DPT) and/or restricted/reduced design rule (RDR). It is the litho-etch-litho-etch (LELE) DPT in which a trim process, a litho-etch (LE) process, follows one or several LE processes. The trim process is used to remove redundant patterns in order to achieve the final patterns corresponding to design intent after forming periodic and lithography-friendly patterns by the preceding LE processes. In addition, it is used to form the narrow gaps between line ends<sup>1</sup>. Since the influence of both the preceding processes and the trim process on the final wafer patterns should be considered through the OPC development, it is necessary to moderate the interference between the OPC developments for the masks and to reduce the increase of required computational resources. The concept of the compact lithography model has been proposed, the results applied to random-logic designs have been shown, and effectiveness of the OPC flow has been discussed.

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