Novel Nonvolatile L1/L2/L3 Cache Memory Hierarchy Using Nonvolatile-SRAM With Voltage-Induced Magnetization Switching and Ultra Low-Write-Energy MTJ

Abstract

To reduce power consumption of CPU, nonvolatile cache memory has been expected by replacing conventional volatile cache memory based on SRAM. This paper describes nonvolatile cache memory hierarchy design using fast and low-power perpendicular (FL-p-) STT-MRAM. For L3, L2 and L1 cache, 1T-1MTJ with FL-p-STT-MRAM, 6T-2MTJ, and short write pulse based 6T-2MTJ having voltage-induced magnetization switching has been presented for the most suitable combination for the cache memory.