Novel NoC Topology Construction for High-Performance Communications

P Ezhumalai,A Chilambuchelvan,C Arun

doi:10.1155/2011/405697

Abstract

Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation.

Highlights

The integration of several heterogeneous components into a single system gives rise to new challenges
Several existing NoC solutions have addressed the mapping problem to a regular mesh-based NoC architecture [1, 2], Ezhumalai et al [2] proposed a survey of architectural design and analysis of network on-chip system computation of regular topologies, FPGA interconnect topologies exploration presented by Marrakchi et al [3], custom NoC architectures with multicast routing are proposed by Yan and Lin [4] and Ezhumalai et al [5] proposed interconnect modeling for improved system-level design optimization, long link insertion techniques for application-specific NoC architectures
The total number of intellectual property (IP) considered for all topologies is 64; the simulation is run for 100000 cycles with asynchronous traffic type

Summary

Introduction

The integration of several heterogeneous components into a single system gives rise to new challenges. With the change of dramatic improvement in this area, it is essential to have an adaptable communication facility that can cope up with the versatile programming of the cores. Such systems will have to process data in real time, perform data transfer at the rate of hundreds of Tbps, support multiple functions and protocols for communications with standard wired and wireless interface, provide security and secrecy and cope up with time-to-market (TTM) pressures and so. Due to exclusive access of shared bus its utilization is as low as 10% This is inflexible to parameters required supporting heterogeneous components of SoC and not scalable.

Interconnection Architectures

Proposed Work

Problem Formulation

Implementation Results