Novel low-voltage BiCMOS digital circuits employing a lateral p-n-p BJT in a p-MOS structure

Abstract

A new BiCMOS buffer circuit and its NAND logic gate implementation for low-voltage environments are presented. The circuit, based on a standard BiCMOS process, employs a lateral p-n-p BJT in a p-MOS structure to trap a charge during the pull-up cycle and using it to speed up the pull-down cycle. The analysis, simulations and SPICE results are based on the submicron technologies and they are used to confirm the functionality of the circuit and evaluate its performance. The comparison with previous circuits is carried out in terms of speed, output voltage swing and power dissipation. The results show that a large voltage swing at a high speed is achievable under 2.2 V operation. The BiFET action in the BiCMOS circuit design has been verified by some experimental results.