Novel In-memory Computing Circuit using Muller C-element

Abstract

Nowadays, von Neumann based computing system is facing a von Neumann bottleneck due to data transfer between separated memory and processor units. Moreover, it results in large energy consumption and reduces overall performance. To solve this von Neumann bottleneck or memory wall, in-memory computing (IMC) has been researched recently. In-memory computing reduces energy consumption and improves performance in von Neumann architecture. This paper proposes a new IMC logic circuit using Muller C-element based on 8 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> T differential static random-access memory (8 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> T SRAM). The circuit provides NAND/NOR/XOR operations simultaneously with 40%, 20%, and 50% faster performance than conventional IMC, respectively.