Novel high-voltage LDMOS with linear graded drift region width

Abstract

In this paper, a novel Lateral Diffused Metal Oxide Semiconductor (LDMOS) with linear graded drift region width is proposed. The device features a specific drift region with the lateral width increasing from source to drain, which modulates the electric field distribution and increases the doping concentration. The breakdown voltage exceeds 600V on the proposed LDMOS with 1μm SOI layer, 3μm buried oxide and 60μm drift region length. The characteristics are investigated by a three dimensional simulator. The simulation results show that a 135% increase in breakdown voltage and 5 times increase in figure of merits are achieved for the proposed device when compared with those of the conventional device.