Abstract
Parallel prefix adders are used for economical VLSI implementation of binary variety additions. The proposed Ling design offers a quicker carry computation stage compared to the standard parallel prefix adders by projecting a replacement methodology to solve Ling adders, which helps to cut the complexity and also the delay of the adder. This paper discusses the look and implementation details for such lower complex, quick parallel prefix adders supported Ling theory of resolving. Specifically, valency or node indicates number of inputs given to a particular node in a carry tree. The proposed ling adder shows that the high-valency Ling adders have superior space area and delay characteristics over antecedent reportable adders for identical input size. Moreover, our 20-bit high valency adder features a higher space and delay measuring than the antecedent used 16-bit adders.
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