Abstract
We presented the ternary logic using a threshold switch (TS) that enabled faster operation than the existing ternary concept and quantitatively compared it to binary logic in a 5-nm node. TS-ternary inverter shows comparable power and performance to the binary inverter in low to high (high to low) operations. Operations passing through the middle state show large delays but still show the fastest speed among existing ternary concepts. Further, our TS-ternary can be applied to various logic applications, and the noise margin can be optimized by adjusting the threshold voltage of the transistor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{T,TR}$ </tex-math></inline-formula> ) and threshold current of TS ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{T}$ </tex-math></inline-formula> ). Moreover, the ternary layout requires a slightly larger area, but the system complexity is reduced to 71.0% compared with binary. Overall, TS-ternary logic is a promising candidate as a future ternary concept, having fast speed, high density, and applicability to diverse logic applications.
Published Version
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