Abstract
This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods.
Highlights
Single Event Effect (SEEs) are undesired erroneous effects in digital integrated circuits caused by ionizing radiation
This paper addresses both Single Event Transients (SETs) and Single Event Upsets (SEUs)
SETs are temporal erroneous signals which originate from the charges generated by the incident particles which are collected by the transistor in a combinational cell
Summary
Single Event Effect (SEEs) are undesired erroneous effects in digital integrated circuits caused by ionizing radiation. The probability of such latching increases proportionally with higher clock frequencies [3,4]. Power consumption and routing complexity is the main concern limiting its usability small or low frequency designs
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