Abstract
In this brief, we present a novel folding technique for high-speed and low-cost Bose–Chaudhuri–Hocquenghem (BCH) decoders. In the conventional BCH decoder, the critical path lies on the Galois-field (GF) multiplier of the key equation solver, where the speedup of the critical path is very difficult due to a significant area increase. In the proposed work, the regularly structured GF multiplier is introduced to be efficiently folded to reduce the complexity and the critical delay. Moreover, the conventional global folding scheme can be applied to further reduce the hardware costs. The implementation results show that the proposed folding scheme enhances the area efficiency by 1.73 and 1.9 times in the Digital Video Broadcasting–Satellite–Second Generation system and the storage controller, respectively.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Express Briefs
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
