Novel flexible buffering architectures for 3D-NoCs

Abstract

In the conventional router architecture of Network-on-Chips (NoCs), each input port employs a set of dedicated flit buffers to store incoming flits. This mechanism unevenly distributes flits among router buffers, which in turn leads to higher packet blocking rates and under-utilization of buffers. In this paper, we address this problem by proposing two novel buffering mechanisms and their corresponding architectures to share flit buffers among several ports of a router efficiently. Our first proposed mechanism is called Minimum-First buffering. This mechanism distributes flits among buffers of input ports based on the number of free buffer slots available in each port, giving priority to minimum occupied buffers. This approach increases the utilization of underutilized buffers by allowing them to store flits of other input ports. The second mechanism (so-called Inverse-Priority buffering) is a lighter yet efficient, flexible buffering technique. This mechanism employs a simple priority order for each buffer. According to our analysis, prioritizing specific ports over others balances the traffic loads between router buffers, and thus yields higher throughput. Both mechanisms lead to lower waiting times in the router and higher utilization in hardware resources. After studying all possible scenarios and analyzing corner cases, we have optimally designed two router architectures equipped with the proposed buffering mechanisms. Moreover, a hardware optimization technique is introduced to reduce the area overhead of the Minimum-First router architecture. The proposed architectures show significant improvements in the performance of 3D-NoCs in terms of the average network throughput and average delay as well as the total number of blocked packets compared to different state-of-the-art and baseline router architectures.