Abstract
Abstract : The primary objective of this Phase I project was to determine the extent of the significant reduction in power consumption of integrated circuits which may be achieved by utilizing a novel sidegate FET technology. The new FET technology eliminates the Narrow Channel Effect (NCE) which is one of the primary factors limiting the minimum power consumption of integrated circuits. By eliminating the NCE, we may scale the device size dramatically and reduce the power-delay product by at least an order of magnitude compared to existing transistor technologies. Additionally, the new FET has two gates which can therefore lead to a significant reduction in the transistor count of ICs, as was demonstrated in a simple NOR gate using only two transistors. Finally, the transistor technology is compatible with fiFET circuits for microwave/digital applications. In this Phase I project, the design, fabrication, characterization and modeling of the new transistor was investigated and issues concerning manufacturability were discussed.
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