Abstract
In this paper, we investigate by simulation and by evaluation of experimental data the feasibility of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect-transistor (FET) structure which is based on our already published Si-nanowire (SiNW) technology. The key technology for this dual-gated general purpose FET contains Schottky S/D junctions on a silicon-on-insulator (SOI) platform. In combination with electrostatic doping and a dual-gate configuration, the Schottky junctions significantly increase the temperature robustness of the device.
Full Text 
Sign-in/Register to access full text options
Sign-in/Register to access full text options 
Published version (
Free)
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
