Novel design of cascaded multilevel inverter with reduced number of components

Abstract

Multilevel inverters are of special importance in high power and medium power applications. Reduced distortion, better output power quality, minimum switching losses, reduced switching stress make multilevel architecture preferred. This paper demonstrates a new topology of a 9-level and 15-level inverters which requires less number of power switches and as well as DC voltage sources than that of existing conventional multilevel inverters (MLI) which results in decreased cost of inverter, switching losses and design complexity. This paper presents simulation results of the inverter system at existing 7 level and proposed9 and 15 levels. The fast Fourier transform (FFT) spectrums of the outputs of 9-level and 15-level inverters are compared. The proposed topology requires same number of switches and DC voltage sources to produce 11-level, 13-level and 15-level outputs. Simulation results show that THD can be decreased by using lesser number of switches.