Novel design for a low-latency CORDIC algorithm for sine-cosine computation and its Implementation on FPGA

Abstract

This paper proposes a design of a fast FPGA based architecture for Coordinate Rotation Digital Computer (CORDIC) algorithm with reduced number of iterations. CORDIC is on such technique which uses just shift-add/sub operations. So, it widely has been used because its flexibility characteristics. However, the major disadvantage is its relatively slow computational speed due to the determination of rotation direction by analyzing the results of the previous iteration. The basic idea of this paper is to reduce the iteration number to overcome this shortcoming. Finally, the prototype based on FPGA architecture has been established to test the performance of the proposed design. The design is implemented in VHDL, synthesized on Xilinx Spartan6 xc6slx9-2tqg144 FPGA kit. The proposed architecture computes Sine and Cosine values in 3/8 n (n is the bit-width of operand) clock cycles and the maximum operating frequency of the proposed architecture is as fast as 108.120 MHz. The simulation and implementation results verify the authenticity of this design.