Novel CMOS Circuits to Measure Data-Dependent Jitter, Random Jitter, and Sinusoidal Jitter in Real Time

Abstract

This paper presents a new zero dead-time architecture for data jitter measurement, which is suitable for on- or off-chip implementations. Two circuits for measurement of data-dependent jitter (DDJ), random jitter (RJ), and sinusoidal jitter (SJ) are demonstrated. The circuits were implemented in a 0.11-mum CMOS process with 1.2-V supply. They utilize a data-to-clock converter, pulse generators, and an integrator followed by a sample-and-hold. The circuits do not require a reference clock, and can demodulate a jittery random binary sequence to output either a DDJ or RJ or SJ waveform in real time. The SJ sensitivity of the circuit with sample-and-hold is 11 muV/ps with an error of 1.56 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> for a 2.5-Gb/s seven-stage pseudorandom binary sequence. The RJ sensitivity of the other circuit without sample-and-hold is 38 muV/ps.