Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance

Abstract

In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips. Advances in integrated circuit technology have led to the birth and proliferation of a wide variety of integrated circuits, including but not limited to application specific integrated circuits, microcontrollers, digital signal processors, general purpose microprocessors, and network processors. ASIC (application specific integrated circuit) technology has evolved from a chip-set philosophy to an embedded core based system-on-a-chip (SoC) i.e. analog and mixed signal chip (AMS)concept. Many applications such as communication devices (VoIP, MoIP, wireless) require chip speeds that may be unattainable with separate IC products. Considering different design constraints, 90% of time is consumed while designing analog block rather than digital block due unavailability of standard analog design tool, also the largest problem is the design constraints of analog circuits are sometimes implicit, which makes porting the design to a new environment difficult and prone to failure. Creating portable analog modules requires the system to capture not only the sized schematic of the circuit but also the objectives that circuit is trying to achieved. This paper applies the embedding knowledge into pure simulation based methodology to perform automatic analog intergraded circuit design, synthesis and optimization in order to reduce development time of this kind of circuits. A practical platform independent computer aided design methodology for synthesis of (analog circuits) Operational Amplifier with flexible noise-power balance is presented in this paper. In order to evaluate the fitness of the circuit specifications in any iteration of SA, NGSPICE simulation is used. The simulation results confirm the efficiency of presented methodology in determining the device sizes in analog circuits.