Abstract

A key aspect in the deployment of electric vertical take-off and landing (eVTOL) aircraft is the safety and performance capabilities of the batteries used. A component of the safety requirements is the need for reserve energy, which would only be utilised in case of emergencies. In the literature, it has been observed that the lower bound of the reserve region of battery energy should be limited to avoid the area where a precipitous drop in voltage would occur. Here, a method for defining the lower bound is proposed. This seeks to extend the amount of time the aircraft can cruise before landing can no longer be completed. A novel power capability testing procedure is used to measure the lowest state-of-charge (SoC) at which a constant power pulse can be completed. This differs from existing power capability tests that perform pulses at predetermined SoC points. The goal of the proposed method is to replicate the conditions of landing to understand the power capability performance at low SoC. The test is performed for a variety of environmental conditions and use cases, which includes temperature and power pulses, as well as two sets of differently aged cells. For the defined test conditions, the lowest SoC values for the calendar aged cells ranges from 6% to 14% SoC, whereas the range for cycle aged cells is 8% to 27% SoC. The outcome of this test is a characteristic map which correlates temperature, pulse power and pulse duration to the lowest SoC the pulse can be completed. The characteristic map indicates the lowest SoC value allowed for the battery before landing needs to be performed. The accuracy of the characteristic map is compared to a battery equivalent circuit model, parametrised from the test data. The defined approaches are experimentally validated based on a set of previously unmeasured experimental conditions. Overall, the characteristic map provides good accuracy compared to measured values, with both map and model methods having an average maximum absolute percentage error of at most 7.5%. Additionally, the test results show that if the worst case landing scenario is used as the lower bound of the reserve region, the useable SoC range for nominal flight would be greatly affected if cell degradation is not considered.

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