Novel Asynchronous Pipeline Architectures for High-Throughput Applications

Abstract

This paper introduces two novel high-throughput asynchronous pipeline methods, suitable for gate-level pipelined systems. The proposed methods, named as early acknowledged hybrid (EA-Hybrid) and high-capacity hybrid pipeline with post-detection (PD-Hybrid), use hybrid data paths that can combine the robustness of dual-rail encoding and simplicity of single-rail encoding schemes. The domino logic style has been adopted for constructing the logic gates in each pipeline stage, as it can provide the latch-less feature. The control path of EA-Hybrid is built based on high-speed early acknowledgment protocol, whereas in PD-Hybrid, it is built based on simple and robust 4-phase protocol. Further, both the proposed pipeline styles allow their logic gates into a special state called the isolate phase in addition to precharge and evaluation phases. The isolate phase leads to improvement in pipeline throughput as well as storage capacity. An 8x8 array multiplier has been designed using the proposed pipeline styles and simulated in three different technologies using UMC libraries. In 180 nm technology, the proposed EA-Hybrid method has achieved 40.25% higher throughput and the pipeline style PD-Hybrid has achieved 18.05% higher throughput than the APCDP.