Novel area-efficient regenerator for driving long on-chip interconnects

Abstract

This paper describes novel small-area low-power regenerator to efficiently drive long on-chip dynamic interconnects. The proposed regenerator requires smaller device count, occupies smaller silicon area, adds less parasitic capacitance to the line, and consumes less power consumption with higher switching speed than conventional regenerators. Comparison results in a 0.18-um CMOS technology indicate that the proposed regenerator achieves up to 65% improvement on power-delay product with up to 56% reduction on silicon area.