Novel Approximate Multiplier Designs for Edge Detection Application

Abstract

Approximate computing in general has garnered much needed attention in the design community owing to high power saving benefits, and at the same time quick generation of results. Approximate computing as a design technique continues to offer design advantages which is recently ceased by the ever decreasing technology scaling. Approximate computing is mostly applied to arithmetic designs, that has resulted in significant research interests. The paper proposes a reliable and efficient approximate multiplier design, that uses optimized lower part constant OR adder (OLOCA) design and hardware optimized approximate adder with normal error distribution (HOAANED) separately as two variants. The two approximate multipliers derived from OLOCA adder and HOAANED adder were found to be highly power and footprint efficient, and in addition offers performance improvement over other approximate multipliers. The error characteristics for the proposed multiplier designs were evaluated and compared with the existing approximate multiplier design. The proposed multiplier design along with the existing ones were synthesized using 45 nm CMOS technology and results were analyzed. The proposed approximate multipliers were further explored for canny edge detection application, and results for different standard images were found to be highly acceptable showing 99.9% of outcome similar to exact multiplier design.