Abstract
A low power and high-speed and highly reliable frequency multiplier for a delay-locked loop-based clock generator is proposed to produce a multiplied clock for different range of frequencies. The high-speed operation and low power consumption can be achieved using modified edge combiner. The proposed frequency multiplier is reducing the delay difference between positive- and negative-edge generation paths and also overcome the deterministic jitter problem. The proposed frequency multiplier is implemented in a 0.13-μm CMOS technology process and achieves power to a frequency ratio of 2.9 μW /MHz, and has the multiplication ratios of 16, and as an output range of 100 MHz-3.3 GHz.
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