Nonvolatile Memory Pre-Silicon Power Loss Test Using FPGA

Abstract

Embedded systems rely on nonvolatile memory (NVM) to retain data in case there is power loss (PL) [1]. However, NVMs that perform program/erase operation of on chip non-volatile bits, the integrity of data stored in NVM itself is susceptible to sudden unexpected PL; especially if PL happens at the instance of NVM bits being updated. In many cases there are field failures in NMVs that are related to PL and due to lack of visibility inside the design, it is very difficult to debug these failures in post silicon. Making NVM chips failsafe from PL is a key design and validation consideration for NVM. Cypress adopted a prevention is better than cure approach to address PL related post silicon failures and focused on rigorous testing in pre-silicon phase, using FPGA. While FPGA validation is common, it is not typical for FPGA based platform to perform PL test. In this paper we present a method where rigorous PL testing was done for Cypress NOR flash NVM product with the goal of zero customer returns from millions of ICs (Integrated Chip) being used in end customer application.