Nonvolatile Delay Flip-Flop Based on Spin-Transistor Architecture and Its Power-Gating Applications

Abstract

We propose and computationally analyze a new type of nonvolatile delay flip-flop (NV-DFF) based on spin-transistor architecture, in which pseudo-spintransistors consisting of an ordinary metal–oxide–semiconductor filed-effect transistor (MOSFET) and a magnetic tunnel junction, referred to as pseudo-spin-MOSFETs are used as a functional nonvolatile storage element. The proposed circuit not only operates as an ordinary DFF, but also is shut down without losing its data. The NV-DFF has only slight increases in circuit delay and layout area within 10% in comparison with an ordinary DFF. Analysis of break-even time (one of the indices for evaluating power-gating efficiency) reveals that the proposed NV-DFF is acceptable for power-gating architecture.