Abstract
The demand for robust computation systems has led to increases in the number of processing cores in current chips. Photonic interconnection has been suggested to facilitate communication in an on-chip infrastructure with a high bandwidth, low power consumption, and scalable structure. A photonic network on a chip can provide interconnections to integrate hundreds of processing cores on a chip, where this structure is suitable for running multiple jobs on a single chip. In this study, we propose a chain of offline multi-job mapping in a photonic network on a chip to improve the delay and power consumption by using a scheduling, allocation, and mapping algorithm. Using the proposed method, the smallest time size first (STSF) scheduling algorithm can be improved by at least 15% in terms of the average waiting time and by 14% for the average response time. Furthermore, with the STSF/ROW/ROW/loss aware (LA) (scheduling/allocation/migration/mapping) schema, the execution time and energy efficiency can be improved by up to 32% and 28 %, respectively.
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