Abstract
This chapter presents a high-speed simulation tool for the design and analysis of pipelined analog-to-digital converters (ADCs) implemented using the Python programming language. The development of an ADC simulator requires the behavior modeling of the basic building blocks and their possible interconnections to form the final converter. This chapter presents a pipeline ADC simulator tool that allows topology selection and digital calibration of the frontend blocks. Several block nonlinearities are included in the simulation, such as thermal noise, capacitor mismatch, gain and offset errors, parasitic capacitances, settling errors, and other error sources.
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