Abstract
This paper present an AC/DC converter topology for sub 0.5 W applications. The presented results are based on preliminary transistor level simulations of the circuit topology in Cadence® Virtuoso® Analog Design Environment. The technology used was a 50 V CMOS process, while the HV devices (400 V) were considered as external components and modelled accordingly. 3 HV MOS devices and 4 external passive components are required by this topology. The simulation results show efficiency more than 70% for two stage configuration, when the rectifier and buck converter is used, and more than 60% for three stage configuration, when the additional low dropout regulator is also used. Moreover, the topology shows a no-load consumption less than 15 mW for both of the configurations.
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