Non‐Conventional Complementary Metal‐Oxide‐Semiconductor (CMOS) Devices

Abstract

AbstractSilicon complementary metal‐oxide‐semiconductor (CMOS) has been the dominating semiconductor technology for over 20 years such that, today whilst the 90‐nm generation is in production the 70‐nm generation is already under development. Currently, many critical device dimensions have reached 1 to 20 nm, and microelectronics is now on a transition to nanoelectronics. In spite of many roadblocks, the ITRS Roadmap expects that Si‐CMOS can be scaled down to the 22‐nm node during the next 15 years. Besides new materials and strain, non‐conventional MOSFETs with thin silicon channels, multi‐gate and 3d structures have the potential to go beyond the planar MOSFET. Already, several architectures, such as fully depleted SOI, wafer‐bonded double‐gate and FinFET have been demonstrated with promising electrical characteristics at gate lengths of 25 to 10 nm. In fact, quantum mechanical simulations predict that these devices can be functional down to 2 nm gate length. Multi‐gate transistors have also been implemented in high‐density Flash memory cells down to 20 nm, and largeVtshifts suitable for multi‐level storage have been achieved. Similarly, for DRAM 3d cell transistors with low leakage currents will be utilized in future. It seems very unlikely that the Si roadmap will end at the 22‐nm node and, assuming that manufacturing and cost issues can be fulfilled, it is most likely that CMOS will continue to dominate in the era of nanotechnology and gigabit systems.