Non-XOR approach for low-cost bit-parallel polynomial basis multiplier over GF(2m)

Abstract

Finite field arithmetic has been widely used in many cryptosystems, particularly in the elliptic curve cryptosystem (ECC) and the advanced encryption standard (AES) as a method for speeding up their encryption/decryption processes. Low-cost design for finite field arithmetic is more attractive for various mobile applications. It is a factor that a large number of Exclusive OR (XOR) gates have been used in the arithmetic operations under the traditional finite field arithmetic implementation. Thus, the cost of the traditional finite field arithmetic cannot be effectively lowered, because a typical XOR gate design consists of 12 transistors. To address this, a novel non-XOR approach consisting of eight transistors, for realising low-cost polynomial basis (PB) multiplier over GF(2 m ) was developed in this study. The authors proposed that non-XOR architecture for bit-parallel PB multiplier uses the multiplexer function instead of the traditional XOR function in its design. Based on the proposed non-XOR methodology, three popular low-cost irreducible polynomials - trinomial, pentanomial and all-one-polynomial - are proposed and designed in this study. The results indicate that the proposed non-XOR architecture can reduce space complexity by 22-, compared with that of the traditional design.