NON-IDEAL CURRENT TRANSPORT IN HETEROSTRUCTURE FIELD EFFECT TRANSISTORS

Abstract

We describe a new analytical model of a Heterostructure Field Effect Transistors (HFETs) that accounts for electron trapping in the gate-drain spacing of the device and for related non-ideal device behavior. Under conditions of a very strong trapping, the electron velocity saturates outside the gate, in the trapping region, and the negative trapped charge leads to relatively large differential output conductance at the drain voltages exceeding the knee voltage. Also under the conditions of severe trapping, the negative trapped charge leads to the positive offset of the output current-voltage (I-V) characteristic. The model describes quite well numerous experimental data for passivated and unpassivated AlGaN / GaN HFETs with and without field plates (FP) under different bias conditions.