Abstract
This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub- read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS) transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and noise data reported from different foundries and technology nodes are used.
Highlights
The idea of an image sensor with photon counting capability is becoming a subject of interest for new applications and imaging paradigms [1,2,3]
In photomultipliers tubes (PMTs) and single photon avalanche photodiodes (SPADs), the electron generated by the incident photon is accelerated and multiplied to a number of electrons from a few hundred in PMTs to millions in SPADs
Low noise CMOS image sensors (CISs) readout chains may include correlated multiple sampling (CMS) that can be implemented with analog circuitry [17,18] or performed after the analog-to-digital converters (ADCs) [19]
Summary
The idea of an image sensor with photon counting capability is becoming a subject of interest for new applications and imaging paradigms [1,2,3] Such a device must have an input-referred read noise negligible compared to a single electron. Sensors 2016, 16, 514 and fill factors of focal plane arrays using such devices They use high voltages, which are not compliant with standard CMOS image sensor (CIS) processes. The read noise has been dramatically reduced to reach deep sub-electron levels [6,7,8]. This paper discusses the possibility of performing photon counting, with standard CIS, essentially from the read noise perspective. This paper shows how the technology downscaling can be used to reduce the read noise and how the gate leakage current could limit this advantage
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