Noise performance optimization design for high-speed analog-to-digital converters

Abstract

An f/sub T/=8.5 GHz NPN bipolar junction transistor (BJT)-based application specific integrated circuit (ASIC) comparator, for use in analog-to-digital converters (ADCs) is designed for optimum noise performance using process-derived model parameters including base spreading resistance, device geometry, and spot noise figure contours. The relationship between sensitivity of the comparator and equivalent input noise (E/sub ni/) and offset voltage (V/sub OS/) is presented. E/sub ni/ and V/sub OS/ must be minimized for a high-resolution comparator. An equivalent input noise voltage of less than 1.2 nV/ square root Hz is predicted and measured, which is approximately 1/3 that obtained from typical low-noise ADC comparators. >