Noise Optimization of Charge Amplifier with MOS Input Transistor Working in Moderate Inversion Region

Abstract

The noise of a fast charge sensitive amplifier (CSA) with an input MOS transistor working in moderate inversion region is discussed. The MOS transistor operation in moderate inversion region becomes especially important in multichannel readout systems, where limited power dissipation is required. The ENC of a CSA followed by a fast shaper is usually dominated by the thermal noise of the input MOS transistor. We perform the noise minimization of such CSA, searching for an optimum input transistor width. The analyses are done using a simplified EKV model and are compared to HSPICE simulations with BSIM3v3 model. We consider several CMOS technology generations with minimum transistor gate length ranging from 0.13 mum to 0.8 mum. We study the sensitivity of ENC to the input transistor width and propose a simple formula to estimate the optimum transistor width, which is valid in a wide range of the input transistor current density