Noise Immunity of Desat Protection Circuitry for High Voltage SiC MOSFETs with High dv/dt

Abstract

This paper provides an analysis of the desat protection for high voltage (>3.3 kV) SiC MOSFETs from the perspective of noise immunity. The high positive dv/dt with long voltage rise time generated by high voltage SiC MOSFETs is identified as a major threat to noise immunity of the desat protection circuitry. The impact of numerous influencing factors is analyzed, such as parasitic inductance, damping resistance, and clamping impedance. In some cases, small parasitic capacitances (<0.01 pF) between the drain terminal with high dv/dt and protection circuitry dominate the noise immunity of the desat protection circuitry with high-impedance voltage divider. The noise immunity margin is derived quantitatively to guide the noise immunity improvement. Different noise immunity enhancement methods are developed and validated with experimental results, including adding a shielding layer, reducing clamping impedance, and decreasing voltage divider impedance.