Abstract
A detailed study of the characteristics of CMOS receiver noise immunity and the effects of skewing CMOS output drivers on simultaneous switching noise was performed. Closed-form equations are given to calculate the simultaneous switching noise and the number of V DD /V SS bond pads-packagem pins in multichip modules. Guidelines for grouping and optimal skewing of CMOS output drivers to reduce the total effective power/ground noise are discussed. Performance trade-offs in using an additional damping resistor in the output driver circuit to reduce power/ground noise were analyzed. Design curves are given to minimize the ‘effective’ switching noise without much trade-off in output driver speed.
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