Abstract
This paper presents circuit techniques and power supply partitioning, filtering, and regulation methods aimed at reducing the phase noise and spurious tones in frequency synthesizers operating in large mixed analog-digital system-on-chip (SOC). The different noise and spur coupling mechanisms are presented together with solutions to minimize their impact on the overall PLL phase noise performance. Challenges specific to deep-submicron CMOS integration of multi-GHz PLLs are revealed, while new architectures that address these issues are presented. Layout techniques that help reducing the parasitic noise and spur coupling between digital and analog blocks are described. Combining system-level and circuit-level low noise design methods, low phase noise frequency synthesizers were achieved which are compatible with the demanding nowadays wireless communication standards.
Highlights
The major trend in nowadays wireless transceivers is towards single-chip CMOS integration
One example of critical magnetic coupling is between the bias bondwire of the voltage controlled oscillator (VCO) and any other aggressor bondwire, which may bring a significant variation of the local VCO supply
The PLL front end consisting of the digital building blocks uses the 1.8 digital supply, since the clock edges are enough fast to be insensitive to the residual supply noise obtained after the high PSRR regulators
Summary
The major trend in nowadays wireless transceivers is towards single-chip CMOS integration. The supply noise and spurs are upconverted around the carrier, degrading the VCO phase noise performance To solve this issue, it has become a standard solution to bias the oscillator from a dedicated high PSRR regulator [1,2,3,4]. It has become a standard solution to bias the oscillator from a dedicated high PSRR regulator [1,2,3,4] Another often encountered example is the coupling to the VCO control line in the applications that use an off-chip loop filter [5, 6]. Bringing the sensitive VCO control node off-chip is very dangerous since any magnetic coupling to the corresponding bondwire directly modulates the VCO frequency and results in spur and phase noise degradation This is the main reason that on-chip PLL loop filters are always preferred.
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