Abstract
In this paper, we present a unique methodology to implement deep IO buffers for Network-on-Chip (NoC) platform, based on a hybrid design involving conventional SRAM and emerging Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) technology. We focus on the system-level impact of probabilistic switching of STT-MRAM devices, arising when write latency of STT-MRAM is reduced through conservative programming and aggressive scaling. We incorporate STT-MRAM specific error detection and correction schemes at the input buffers, and propose a new limited flit retransmission scheme to reduce flit errors due to the probabilistic switching. Our hybrid STT-MRAM buffers along with additional logic consume less than 80% of the area of SRAM-only FIFOs of the same depth. We demonstrate optimum NoC throughput at moderate injection rates on a mesh NoC.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
