Nickel Silicide and Nickel Germanosilicide Processing in a Near-Isothermal Cavity: Sheet Resistance Curves for Blanket Ni/Si and Ni/SiGe Substrates and Electrical Data for CMOS Devices

Abstract

NiSi has become the preferred material in CMOS technology for source and drain contacts and is being considered as a metal gate material as well. With strain engineering demanding different types of strain for NMOS and PMOS transistors, Ni metal reacts with substrates that have a wide variety of properties (i.e. chemical composition, doping level, different crystalline phases). All of the relevant material combinations need to be taken into account when designing and optimizing an IC manufacturing process. The first part of this study was performed on 300 mm diameter blanket wafers and focuses on Ni metal reactions with lightly doped single-crystal Si and Si0.8Ge0.2. The former is typically used for sources and drains for NMOS transistors (need tensile stress in the channel for electron mobility enhancement), the latter for PMOS transistors (need compressive stress in the channel for hole mobility enhancement). The phase transformation curves for Ni/Si and Ni/Si0.8Ge0.2 are used for identifying the IC process window. In the second part of this study, we used 300 mm diameter device wafers (K8 microprocessor, 65 nm design rule) and targeted four distinct annealing conditions that were chosen based on the blanket wafer experiments.