Abstract
Software design tools, such as compilers and simulators, are widely used in the integrated circuits (IC) industry. As the circuit complexity grows, better and faster tools are required. One way to speed up a software system is to parallelize it and execute it on multiple CPUs. This idea is particularly appealing when it comes to the compilers for hardware description languages (HDL). In this paper, we explore the parallelization of a Verilog compiler on a network of computers using Parallel Virtual Machine (PVM). Our design parallelizes the three most important and time-consuming phases of the compilation process while minimizing the communications overhead. Experimental results reveal that the algorithms used for parallelizing the compiler results in a speedup of the compilation process.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
