New Switched-Multi-Source Inverter Topology with Optimum Number of Used Switches

Abstract

In this paper, a new Switched-Source Multilevel Inverter (SSMLI) topology is proposed. The new topology outperforms existing SSMLI topologies by reducing the number of switches required to generate a voltage level, presenting a lower voltage stress on the switches, and thus making the inverter more cost- and size-efficient. The proposed topology also presents a lower number of switches in the current path, which can be interpreted as an improvement on the total power loss of the inverter. The basic unit is comprised of two power sources and six switches. As standalone, it is capable of generating 5-level output voltage in symmetric mode (i.e., equal-value power sources), and 7-level output voltage in asymmetric mode (i.e., unequal-value power sources). When $m$ number of basic units are cascaded, the inverter can generate up to 2m+ 1 + 1 output voltage levels for symmetric-mode operation and 22m+1-1 (m = 1,2,3, …) for asymmetric-mode operation. Simulation results using Mat-lab/Simulink for 7-level output voltage (1 cascaded unit) and for 31-level output voltage (2 cascaded units) are presented here, and they successfully validate the performance of the proposed topology.